Microkernel Architecture-based Real-Time Operating System
High-performance microkernel designed for embedded systems, supporting ARM Cortex-M / RISC-V architectures, providing deterministic real-time response and capability-based security.
Priority-based preemptive scheduling, microsecond-level interrupt response, deterministic task execution.
Capability-based access control, principle of least privilege, preventing unauthorized access.
Efficient inter-process communication supporting synchronous/asynchronous message passing.
Clear kernel module separation, easy to extend and customize.
Minimal memory footprint, suitable for resource-constrained embedded devices.
Supports ARM Cortex-M and RISC-V architectures, easy to port.
Application processes interact with the kernel via system calls and receive event notifications through IPC.
Provides core services including thread management, IPC, capability control, memory management, scheduler, and interrupt handling.
Hides hardware differences and provides a unified hardware access interface.
Thread creation, scheduling, state management and context switching. Supports 256 priority levels with priority inheritance protocol.
TCB_Create | TCB_Start | TCB_Suspend | TCB_Resume
Endpoint-based message passing mechanism supporting synchronous calls, asynchronous notifications, and non-blocking operations.
IPC_Send | IPC_Recv | IPC_Call | IPC_Reply
CNode-based capability management supporting capability copy, derivation, revocation, and access control.
CNode_Copy | CNode_Mint | CNode_Revoke
Physical page allocation, virtual memory mapping, and address space management with MPU protection.
Page_Alloc | Page_Map | Page_Unmap
Fixed-priority preemptive scheduling with Round-Robin at same priority level, supports periodic budget management.
Scheduler_Yield | Scheduler_Tick
IRQ binding, priority management, and interrupt dispatch. Notifies user threads via Notification.
IRQ_Bind | IRQ_Enable | IRQ_Disable